1. Field of the Invention
The present invention relates to semiconductor integrated circuit (hereinafter abbreviated as IC) structures, and more particularly, to semiconductor IC structures of inverter (hereinafter abbreviated as INV), 2-input not- and gate (2-input NAND, hereinafter abbreviated as ND2) and 2-input exclusive- or gate (hereinafter abbreviated as XOR2).
2. Description of the Prior Art
Fabrication of microstructures requires tiny elements of precisely controlled size formed in a material layer of an appropriate substrate such as semiconductor substrate/layers, dielectric layers and/or metal layers. These tiny elements are generated by patterning the abovementioned substrate/layers, for instance, by performing photolithography and etching processes. For these purposes, in conventional semiconductor techniques, a mask layer is formed on the material substrate/layers, and these tiny elements are defined in the mask layer and followed by being transferred to the objective material substrate/layers. Generally, the mask layer may include or is formed by means of a layer of photoresist that is patterned by lithographic process and/or patterned hard mask including the patterns transferred from the patterned photoresist. Since the dimensions of the patterns in sophisticated ICs are steadily decreasing, the equipment used for patterning devices features have to meet very stringent requirements with regard to resolution and overlay accuracy of the involved fabrication processes. In this respect, resolution is taken as a measure specifying the consistent ability to print minimum images under conditions of predefined manufacturing variations.
As feature sizes are decreased under 85 nanometers (hereinafter abbreviated as nm), the existing single patterning process has met its bottleneck to successfully render the features. In order to push the lithographic limit further and to create even smaller, more densely packed devices, multiple patterning technology such as double patterning process, are being developed with presently available manufacturing equipment. Typically, the multiple patterning technologies are to decompose dense layout patterns into sub-patterns and then use two or more masks to print each sub-pattern. By transferring the sub-patterns to the photoresist layer/mask layer, the wanted patterns are re-constructed and obtained.
It is found that the multiple patterning technology gives rise to process control challenges. Thus, process complexity and process cost are unavoidably increased with the involvement of the multiple patterning technology.
More important, the ICs have been one of the most important hardware used in the modern information society, and the ICs having complex functions are made up of many standard cells, each with basic functions. Since those standard cells are essential elements for the ICs, layout structures of those standard cells enormously affect the whole layout structure of the ICs. It is therefore always in need to provide semiconductor IC structure(s) that is able to improve process yield and to reduce process complexity.